Field
Embodiments of the present disclosure generally relate to methods and apparatus for forming fin field-effect transistor (FinFETs) structures. More specifically, embodiments described herein relate to fin structure formation by selective etching and deposition processes.
Description of the Related Art
In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures have been developed. An example of such devices may include FinFETs having conductive fin-like structures that are raised vertically above a horizontally extending substrate. Conventional FinFETs may be formed on a substrate, such as a semiconducting substrate or silicon-on-insulator substrates. The substrate may comprise a semiconducting substrate and an oxide layer disposed on the semiconducting substrate.
When manufacturing FinFETs, it is desirable to have a fin structure with a high aspect ratio. A higher aspect ratio for the fin structure allows a larger amount of current to be provided through the same amount of topographical area. Fabrication of high aspect ratio FinFETs is difficult as a result of the reduced critical dimensions required for sub-10 nm nodes. Forming sub-10 nm node FinFET structures is further complicated by limitations and increased complexities of various patterning and lithography processes.
For example, multiple patterning processes, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) processes, may not adequately provide reliable patterning given the small pitch size requirements associated with formation of sub-10 nm node FinFET structures. Other lithography processes, such as litho-etch-litho-etch (LELE) processes which utilize 193 nm immersion photolithography, may increase the line width roughness (LWR) of a resist used to pattern features on the substrate. The increase in LWR may lead to variations in threshold voltages, such as “hot spots” or areas of lower resistance, of the subsequently formed fin features and ultimately result in poor device performance. Moreover, current lithography and patterning processes are time consuming, which reduces throughput for device processing.
Thus, what is needed in the art are methods and apparatus for manufacturing FinFET structures.